Description[ edit ] The x87 registers form an 8-level deep non-strict stack structure ranging from ST 0 to ST 7 with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped. The non-strict stack model also allows binary operations to use ST 0 together with a direct memory operand or with an explicitly specified stack register, ST x , in a role similar to a traditional accumulator a combined destination and left operand. This can also be reversed on an instruction-by-instruction basis with ST 0 as the unmodified operand and ST x as the destination. These properties make the x87 stack usable as seven freely addressable registers plus a dedicated accumulator or as seven independent accumulators. This is especially applicable on superscalar x86 processors such as the Pentium of and later , where these exchange instructions codes D9C Despite being natural and convenient for human assembly language programmers, some compiler writers have found it complicated to construct automatic code generators that schedule x87 code effectively.
|Published (Last):||9 April 2007|
|PDF File Size:||1.75 Mb|
|ePub File Size:||16.44 Mb|
|Price:||Free* [*Free Regsitration Required]|
Compared to typical software-implemented floating point routines on an without an , the factors would be even larger, perhaps by another factor of 10 i. Architectural generations Main article: Intel The was the first math coprocessor for bit processors designed by Intel the I was older but designed for the 8-bit Intel ; it was built to be paired with the Intel or microprocessors.
It is incapable of operating with the , as the has a 8 bit data bus; the can only use the The did not appear at the same time as the and , but was in fact launched after the and the Later followed the iXL with microarchitecture and the iXLT, a special version intended for laptops, as well as other variants.
The XL was actually an SX with a pinout. The and XL worked with the microprocessor, and were initially the only coprocessors available for the until the introduction of the in However, for both of these chips the was strongly preferred for its higher performance and the greater capability of its instruction set.
The limited the argument range to plus or minus 45 degrees. Without a coprocessor, the normally performed floating-point arithmetic through slow software routines, implemented at runtime through a software exception-handler.
When a math coprocessor is paired with the , the coprocessor performs the floating point arithmetic in hardware, returning results much faster than an emulating software library call. The i was compatible only with the standard i chip, which had a bit processor bus.
EFlags The processor was a significant evolution in the x86 architecture, and extended a long line of processors that stretched back to the Intel The predecessor of the was the Intel , a bit processor with a segment -based memory management and protection system. The added a three-stage instruction pipeline, extended the architecture from bits to bits , and added an on-chip memory management unit. This paging translation unit made it much easier to implement operating systems that used virtual memory.
Aragami File:KL Intel Discontinued BCD oriented 4-bit I, the copyright holder of this work, hereby publish it under the following licenses:. Like other extensions to the basic instruction set, x87 instructions are not strictly needed to construct working programs, but provide hardware and microcode implementations of common numerical tasks, allowing these tasks to be performed much faster than corresponding machine code routines can. Wikimedia has received an e-mail confirming that the copyright holder has approved publication under the terms mentioned on this page. Also, to clarify, the only difference between a SX and DX is a bit vs. Intel SX Such a stack-based interface potentially can minimize the need to save scratch variables in function calls compared with a register-based interface  although, historically, design issues in the intrl implementation limited that potential.